The fabrication of metal-oxide-semiconductor (MOS) transistors within a semiconductor substrate is well known. These MOS transistors include a plurality of polysilicon gate structures that are formed over lightly doped drain implants that are conducted to form source and drain regions. After formation of the polysilicon gates, a source/drain implant is then performed to complete the source/drain regions. In a p-type channel MOS device, boron is most often used to implant the source/drain regions.
As transistor channels shrink below 50 nm the limitations of conventional transistor processing, associated with such boron implants, has become more apparent. To combat short channel effects in these transistors, the depth of the source/drain junctions and more importantly the thicknesses of the gate oxide has been reduced. However, as the gate oxide thickness has decreased, devices have become more susceptible to diffusion of boron dopants through the gate oxide and into the active area of the transistor. The presence of these dopants within the channel region, can undesirably alter the threshold voltage of the device and may cause the device to be unstable due to threshold voltage drifting. This problem is especially acute for boron implanted gate structures.
In addition to reliability concerns, thin gate oxides present significant manufacturing challenges as well. The uniformity of the gate dielectric film across the wafer has become more critical as the film thickness has decreased. A 0.2 nm variation in film thickness across a wafer is far more significant in a 2 nm film than in a 5 nm film.
In the past, the semiconductor manufacturing industry attempted to prevent boron penetration within transistor structures in two ways. The first way includes manufacturing the transistor structure containing an oxide/nitride stack. The concept is to put a silicon nitride layer between an oxide layer and a poly gate layer. If the silicon nitride layer has a minimum thickness of 0.7 nm, the boron penetration tends to be retarded. However, at silicon nitride thicknesses less than 0.7 nm, which is the current trend, the boron continues to penetrate into the active device regions. Moreover, an interfacial charge of about 1E11/cm2 is present at the silicon nitride and oxide interface. When the silicon nitride and oxide are thick, this is not a problem; however, as the thickness of the gate oxide continues to decrease, this interfacial charge decreases device performance and may even cause the device to malfunction completely.
A second way the semiconductor manufacturing industry has attempted to reduce boron penetration, while continually decreasing the oxide thickness, is to grow a silicon dioxide layer as the gate oxide and anneal the silicon dioxide layer with nitrous oxide and heat. The method prevents boron from penetrating into the active device region; however, because the oxygenated region is at the interface between the silicon substrate and the silicon dioxide layer, the boron penetrates deep enough to cause device mobility problems. Likewise, as discussed above, an interfacial charge of about 5E10/cm2 is present at the silicon dioxide silicon substrate interface, which also affects the device performance.
Accordingly, what is needed in the art is a transistor device having a structure sufficient to prevent boron penetration from the poly gate to the active device regions without experiencing the problems that the prior art transistor structures experience during boron doping of the poly gate.